Solar PV Grid Tied Inverter Fault Detection Techniques


  • An international research group has conducted a comprehensive analysis of all failure modes and vulnerable component faults in grid-connected solar inverters that offers a broad view of all available detection and localization techniques.

The overview provides, in particular, a classification of various component failure modes and their potential causes in a tabular form and describes different approaches for data preparation and feature mining. It also categorizes all fault detection and localization (FDL) techniques in a tabular manner.

The review includes a list of all wear-out failures such as bond-wire heel cracks, solder fatigue, die-attach degradation and delamination, aluminum reconstruction, substrate cracks, corrosion, electrochemical migration, ionic contamination, and time-dependent dielectric breakdown. It also categorizes catastrophic failures such as latch-up, bond-wire melting, avalanche breakdown, electrostatic discharge, and secondary breakdown.

Furthermore, the work analyzes the impact of these failures on the performance of solar modules and the inverter themselves, as well as a description of both model-based and model-free FDL approaches and other FDL techniques.  Model-free methods coupled with artificial intelligence (AI) were found to be the most efficient in terms of quantifying the performance parameters. “In addition, AI based techniques provide superior detection and localization abilities as compared to model-based techniques,” the academics explained. “However, a bottleneck in the direction of AI is that there are very few real-time implementations of AI based techniques.”

Their work was presented in the paper Overview of Fault Detection Approaches for Grid Connected Photovoltaic Inverters, which was recently published in e-Prime – Advances in Electrical Engineering, Electronics and Energy. The research group includes scientists from the Jamia Millia Islamia University in India, the Brno University of Technology in Czechia, and the Aalborg University in Denmark. “The future work is further motivated to include the inductance estimation in current emulators as a part of new fault detection approaches and improve the efficiency under high power operation,” they concluded.

Author: Emiliano Bellini

This article was originally published in pv magazine and is republished with permission.

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